Test Patterns

DS1 Test Patterns:

1IN8 (Sometimes called 1:7)

2IN8

3IN24

ALLONES (Framed)

ALLZEROS (Framed)

QRS

53 Octet (T1-5)

54 Octet (T1-3)

55 Octet (T1-6)

72 Octet (T1-1)

96 Octet (T1-2)

120 Octet (T1-4)

IBM 80 Zeroes

DALY (a modified 55 Octet to be used on AMI circuits)

TRIP (a modified T1-2 96 octet – not to be confused with TTC T1-2)

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GENERAL PURPOSE FIXED TEST PATTERNS

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1:1 Pattern: A repeating pattern of alternating ones and zeros.

This pattern provides minimum stress on timing recovery circuits, and maximum stress to switching type power supplies. It is also the pattern to use when a 50% duty cycle pattern is needed, such as when running a Nyquist line loss test on a DDS access facility.

If loaded into a test set USER pattern to ensure DS1 frame bits fall at octet boundaries, this would be:

Binary: 01010101 [LtR], Hex: AA [RtL]

In theory Binary: 10101010 [LtR], Hex: 55 [RtL] could be used as the USER pattern, except this frame aligns with bit 2 being a ’0′ which creates a false Yellow Alarm an a D4 framed T-1. Except on a D4 frame T-1, frame alignment with this pattern is normally not critical so the 1:1 pattern built into most test sets is usually adequate.

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1-in-8: fr 01000000 [LtR]/Hex: fr 02 [RtL]

Only a single one in a repeating 8-bit sequence. Stresses timing recovery circuits, and provides 12.5% ones density for AMI facilities. Some texts refer to this as the 1-in-7, or 1:7, pattern because there is one ’1′ and seven ’0′s. Used with the 2-in-8 pattern to verify proper operation of B8ZS line coding on equipment optioned for it. Whenever a ’0′ frame bit occurs there will be eight zeros in a row for the channel 24 time slot. This will cause B8ZS to invoke, and the B8ZS indicator on a test set to blink.

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2-in-8: fr 01000010 [LtR]/Hex: fr 42 [RtL]

Stresses Timing Recovery and ALBO circuits. Since eight consecutive zeros cause a B8ZS substitution on a DS1 configured for it, and this pattern has a maximum of 4 consecutive zeros, IT WILL NEVER INVOKE B8ZS.

This pattern is used with the 1-in-8 pattern to verify proper operation of a circuit with B8ZS line coding. If a B8ZS line code indication is received while running this pattern on a DS1 there is definitely a problem. It may be BPVs from the local loop, a local hardware problem, an ALBO problem, or a bad test set.

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All 1′s (MARK) Pattern: fr 11111111 [LtR]/Hex: fr FF [RtL]

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**

* WARNING: AN ALL 1′S CONDITION ON MULTIPLE DS1′S IN THE SAME REPEATER

SHELF*

* CAN CREATE HIGH CURRENT DRAW FROM THE SHELF POWER SUPPLY WHICH CAN DAMAGE

*

* PERFECTLY GOOD EQUIPMENT IF LEFT UP FOR TOO LONG. THIS IS WHY BELLCORE

*

* DOCUMENTS STATE THIS PATTERN IS TO BE USED FOR NO MORE THAN TWO MINUTES.

*

* USE THE T1-4/120 OCTET PATTERN FOR LONGER TERM HIGH 1′S DENSITY TESTING.

*

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**

All 1′s (MARK) Pattern: (Continued)

This pattern makes repeaters and other active devices draw maximum current from their power supplies. If the DC current draw exceeds the capabilities of the power supply, either because it is defective or under-sized, errors will occur in a short time. Always remember, many power supplies have two current ratings, continuous and peak. The peak rating is normally time rated, and pulling peak current for long periods can damage perfectly good equipment.

FRAMING MUST BE ON WHEN THE ALL 1′S PATTERN IS USED ON DS1 CIRCUITS!!

An unframed all 1′s pattern is seen as an Alarm Indication Signal (AIS) by many types of equipment and systems. Not using framing WILL cause false network alarms – and earn you the wrath of Network Surveillance.

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All 0′s (SPACE) Pattern: fr 00000000 [LtR]/Hex: fr 00 [RtL]

For finding AMI/B8ZS mismatches, and AMI/AMI patches, on circuits that are supposed to use B8ZS line coding. It can stress timing recovery circuits of CSUs, DSU/CSUs, MODEMs, repeaters, etc., beyond their limits causing such equipment to lock up and require being power cycled to restart.

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* WARNING: WHEN RUN ON DS1 or DS0/Nx64 FT1 CIRCUITS, THE END-TO-END PATH *

* MUST USE B8ZS LINE CODING, OR TRAFFIC AFFECTING FAILURES MAY OCCUR. *

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This pattern is not recommended for general DS1 testing and should only be needed if RC-28D or RC-48D M13s, that can handle more than 80 zeros, are on the circuit. For other M13′s the ’80-Zeros’ pattern is recommended to reduce the likelihood of DS1 port ‘lock-up’ when there are no signals present on the other ports of a DS2 card. This ‘lock-up’, or ‘going to sleep’ of a DS1 port when the All Zeros pattern is run is most likely when an AMI/AMI patch occurs, where even the transitions from the B8ZS BPVs are not present rather than an AMI/B8ZS mismatch situation.

When this happens, the DS2 will output all zeros on all of its DS1′s which can create the impression there is no problem. While a pattern containing transitions, as well as lots of zeros would have found one. If the All Zeros pattern is used on a DS1, also use the 80-Zeros pattern as a double check.

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3-in-24: fr 01000100 00000000 00000100 [LtR]/Hex: fr 22 00 20 [RtL]

This version of the pattern has been accepted by BellCore and the NOF.

Some people call this, “The Modified 3-in-24 Pattern,” because it is a change to the original 3-in-24, needed to correct problems seen when running framed on AMI facilities. The pattern shown is now the ACCEPTED PATTERN, not a modification of the accepted pattern. You should be aware there are still some non-standard “Modified” versions floating around.

This pattern contains the longest string of consecutive zeros (15), with the lowest ones density (12.5%) allowable for AMI coding. Bit 2 of every third byte is set to a ’1′, which should prevent false Yellow Alarms. It will NOT violate the 1′s density rules for AMI when run framed, and should normally be used that way. It will invoke B8ZS on equipment optioned for it.

3-in-24: (Continued)

It stresses Timing Recovery circuits, and is effective in finding AMI/B8ZS equipment mismatches when run head-to-head. Because most equipment optioned for AMI will pass 15 zeros with no problem, it is not as effective in finding AMI-to-AMI patches. As noted in the introduction, loop testing will only find mismatches from one side of the AMI/B8ZS patch. A loop test from the other end will be perfectly clean. This is true for all patterns used to find mismatches.

There are several issues related to the 3-in-24 test you must be aware of.

Otherwise you may create problems, or end up chasing nonexistent ones:

(a) In some documents Hex 22 00 02 (Binary 01000100 00000000 01000000) is shown instead of Hex 22 00 20. This does set bit 2 of every other byte to a ’1′, preventing false Yellow Alarms. The problem is, it only has 11 zeros in a row. This will not provide the maximum stress to AMI facility timing recovery circuits. This 22 00 02 Hex pattern is most likely the result of a typo.

(b) Some Telco’s still have older T-Berd 209 test sets with the original

3-in-24 pattern built in. When run framed on AMI circuits the 1′s density rule is violated whenever a ’0′ frame bit is added to the 15 zero part of the pattern. Bit 2 is also held as a ’0′ in all bytes, simulating a Yellow Alarm to equipment that can detect it. If a Telco tester insists the 3-in-24 test must be unframed or errors will occur, or when testing across the network other patterns are clean but 3-in-24 starts Yellow Alarms, it is a pretty good tip-off an older test set is being used. If this is the case, have the accepted pattern loaded as a USER, or PROGRAMMABLE, pattern and use it to test with.

(c) In an attempt to avoid the above problem, some Telco’s came up with the ‘Modified’ pattern of:

fr 00100010 00000000 00000010 [LtR], Hex fr 44 00 40 [RtL].

This does stop the 1′s density violation problem, but bit 2 is still held as ’0′, so a false Yellow Alarm will occur on SF facilities. If a Telco suggests this pattern as an alternative to running 3-in-24 unframed, give them the accepted pattern instead.

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PSEUDO RANDOM BINARY SEQUENCE (PRBS) TEST PATTERNS ======================================================

These signals consist of a bit sequence that approximates a random signal generally considered to emulate customer traffic. A PRBS is generated by an (n)-stage shift register with feedback loops. The PRBS will be 2E(n)-1 bits in length, such as the 2E15-1, 2E20-1, and 2E23-1 patterns.

These patterns cycle between maximum ones density (one ’0′ and 14, 19, or

22 ’1′s), and minimum ones density (one ’1′ and 14, 19, or 22 ’0′s), with ‘random’ combinations of ’1′s and ’0′s in-between.

Some details on the individual patterns:

63 (2E6-1):

Longest sequence of zeros unframed (DS0): 5

Longest sequence of zeros framed (DS1): 6

Longest sequence of ones unframed (DS0): 6

Lowest stress of any PRBS pattern.

Useful for testing DS0s at speeds below 9.6kb/s.

Will run on DS1 facilities using AMI line coding.

Will NOT invoke B8ZS on DS1 facilities configured for it.

Starting pattern for Round-Trip Delay measurements.

511 (2E9-1):

Longest sequence of zeros unframed (DS0): 8

Longest sequence of zeros framed (DS1): 9

Longest sequence of ones unframed (DS0): 9

Useful for testing DS0s at speeds below 9.6kb/s.

Will run on DS1 facilities using AMI line coding.

Will invoke B8ZS on facilities configured for it.

Second pattern for Round-Trip Delay measurements.

2047 (2E11-1):

Longest sequence of zeros unframed (DS0): 10

Longest sequence of zeros framed (DS1): 11

Longest sequence of ones unframed (DS0): 11

Useful for testing DS0s at speeds between 9.6 and 56kb/s.

Will run on DS1 facilities using AMI line coding.

Will invoke B8ZS on facilities configured for it.

Third pattern for Round-Trip Delay measurements.

2E15-1: 32,757 bits in length.

Longest sequence of zeros unframed (DS0): 14

Longest sequence of zeros framed (DS1): 15

Stresses ALBO, equalization, and timing recovery circuits.

Will run on DS1 facilities using AMI line coding.

Will invoke B8ZS on facilities configured for it.

Alternate pattern for DS1 jitter measurements.

Fourth pattern for Round-Trip Delay measurements, if needed.

2E20-1: 1,048,575 bits in length

Longest sequence of zeros unframed (DS0): 19

Longest sequence of zeros framed (DS1): 20

Stresses ALBO, equalization, and timing recovery circuits.

NORMALLY USED ONLY ON DS1 FACILITIES WITH B8ZS LINE CODING.

Will invoke B8ZS on facilities configured for it.

Used to check the excess zero capability of an OUT OF SERVICE AMI DS1.

Fifth pattern for Round-Trip Delay measurement, if needed.

QRSS: – This is actually the 2E20-1 pattern modified to transmit a

maximum of 14 zeros.

Pseudorandom sequence based on a 20-bit shift register. Generates every

combination of 20-bit words, repeats every 1,048,575 bits, and suppresses

consecutive zeros to no more than 14. Keep in mind that on a 9.6Kb/S

circuit it will take just under two minutes for ONE complete sequence

through this pattern.

It contains high ones density sequences, low ones density sequences, and

sequences that change rapidly between the two. This is the standard

pattern suggested for performing DS1 jitter measurements. It will invoke

B8ZS on equipment optioned for it, has a 50% average ones density, and

generates blocks of zeros as shown:

CONSECUTIVE ZEROS NUMBER OF TIMES PER SEQUENCE

—————– —————————-

14 32

13 32

12 64

11 128

10 256

09 512

08 1,024

07 2,048

06 4,096

05 8,192

04 16,384

03 32,768

02 65,536

01 131,072

2E23-1: 8,388,607 bits in length

Takes over 2 min. to complete at 56kb/s.

Longest sequence of zeros unframed (DS0): 22

Longest sequence of zeros framed (DS1): 23

Stresses ALBO, equalization, and timing recovery circuits.

USE ONLY ON DS1 FACILITIES WITH B8ZS LINE CODING.

Will invoke B8ZS on facilities configured for it.

Useful for locating AMI/B8ZS and AMI/AMI patches when run head-to-head.

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DDS-x FIXED TEST PATTERNS

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DDS-x TEST PATTERNS:

As the name implies, these patterns are intended for testing DDS DS0 circuits. Be extremely careful when testing Nx64 contiguous band width circuits. Check that the circuit is on B8ZS facilities BEFORE running the test. FAILURE TO DO SO, AND RUNNING THE PATTERNS CONTAINING 100 BYTES OF HEX ’00′ MAY CREATE A TRAFFIC AFFECTING EXCESS ZEROS PROBLEM ON AMI FACILITIES RESULTING IN A TRAFFIC AFFECTING FAILURE OF THAT FACILITY.

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DDS-1 Pattern: 100 Octets of all ones, followed by 100 Octets of all zeros.

In Hex [RtL]:

FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

This pattern switches rapidly between maximum and minimum ones density, creating extreme stress on power supplies and regulators, timing recovery circuits, ALBO circuits, and repeater equalization circuits. REMEMBER – 100 HEX BYTES OF ’00′ IS 800 BINARY ZEROS IN A ROW. RUNNING THIS PATTERN ON A DS1, OR Nx64, CIRCUIT RIDING AMI LINE CODED FACILITIES CAN RESULT IN A TRAFFIC AFFECTING FAILURE OF THAT FACILITY.

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DDS-2 Pattern: 100 Octets of 01111110, followed by 100 Octets of all zeros.

In Hex [RtL]:

7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 7E 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

This pattern switches rapidly between HDLC/SDLC protocol 7E ‘flags’, or idles, and all zeros. It will find some ‘Pattern Sensitivity’ problems related to HDLC/SDLC protocols. It also provides extreme stress to timing recovery, ALBO, and repeater equalization circuits with the ’00′ portion of the pattern. Most HDLC/SDLC protocol ‘Pattern Sensitivity’ problems occur when the ’7E’ flag follows a long string of ones. So some of the Special Purpose Fixed Test Patterns may be more useful for finding such problems.

AGAIN, REMEMBER – 100 HEX BYTES OF ’00′ IS 800 BINARY ZEROS IN A ROW.

RUNNING THIS PATTERN ON A DS1, OR Nx64, CIRCUIT RIDING AMI LINE CODED

FACILITIES WILL RESULT IN A TRAFFIC AFFECTING FAILURE OF THAT FACILITY.

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DDS-3 Pattern: Repeating pattern of Binary: 00110010 [LtR], Hex: 4C [RtL]

This pattern is a traffic simulator that stresses power supplies and regenerator switching circuitry with very rapid transitions between ones and zeros. This pattern will run safely on all DS1 facilities if loaded as a USER pattern, but will NOT cause B8ZS to invoke on circuits configured for it.

NOTE: FireBerd 6000 test sets prior to Rev. J transmitted this pattern Left-to-Right. This created problems when running with other test sets.

This was corrected in Rev. J, which transmits the hex Right-to-Left.

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DDS-4 Pattern: Repeating pattern of Binary: 01000000 [LtR], Hex: 02 [RtL]

This pattern provides the minimum required ones density for a DS0 DDS circuit. It stresses timing recovery and repeater equalization circuitry.

This pattern will run safely on all DS1 facilities, but the true 1-in-8 pattern is preferred. The reason is most test sets that allow DDS-x test patterns to be run through the DS1 interface do not frame align the DDS patterns. This means the frame (fr) bits do not always fall at octet boundaries. The true 1-in-8 pattern will be frame aligned, so no framing bits will end up in the middle of an octet.

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DDS-5 Pattern: A compilation of DDS patterns 1-4 (See NOTE under DDS-6)

This pattern runs DDS-1 through 4 in rapid sequence, without having to option the test set and restart the test between each one. Use the individual patterns to find the possible cause of the problem if errors are seen with this pattern.

WARNING: BOTH DDS-1 AND DDS-2 CONTAINED IN THIS PATTERN HAVE 100 BYTES OF HEX ’00′ (800 BINARY ZEROS IN A ROW). RUNNING THIS PATTERN ON A DS1, OR Nx64, CIRCUIT RIDING AMI LINE CODED FACILITIES WILL RESULT IN A TRAFFIC AFFECTING FAILURE OF THAT FACILITY.

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DDS-6 Pattern: An 8 Octet repeating pattern consisting of: (See NOTE

below)

Binary [LtR]:

11111110 11111110 11111110 11111110 11111110 11111110 11111110 11111111

Hex [RtL]: 7F 7F 7F 7F 7F 7F 7F FF

This pattern is a simulation of the transition from IDLE mode to DATA mode on a DDS circuit. It is used to detect marginal equipment in multipoint applications and will stress power supplies and ALBO circuits. This pattern will run safely on all DS1 facilities. Like the T1-4 pattern, it is a legal ‘work around’ to the two minute limit for the ‘All Ones’ pattern on DS1 circuits.

NOTE: FireBerd 6000s prior to Rev. J have the DDS-1 through DDS-4 compilation identified as DDS-6, and the DMI Idle pattern identified as DDS-5. This was corrected in Rev. J to conform to the standards set by the NOF, which state the DDS-1 through DDS-4 compilation will be called DDS-5. For example, to run the DDS-1 through DDS-4 compilation pattern head-to-head between a Rev. J and a Rev. H test set, the Rev. J would use DDS-5 and the Rev. H would use DDS-6.

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TDS T1-x FIXED TEST PATTERNS

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The T1-x patterns are by definition primarily intended for use in testing

T1 circuits. They provide similar functions on contiguous bandwidth Nx64 and

Nx56 DS0 circuits when loaded as USER patterns. The T1-x patterns with rapid changes from high-ones to low-ones density are also useful in finding marginal DS0-DP and OCU-DP cards on DS0A circuits when loaded as USER patterns. The T1-x patterns built into a TTC FireBerd 6000 are intended for use with the

T1

interfaces only. They are not compatible with the DDS interfaces.

Be aware that the T1-x designations for these patterns were assigned by TTC Corporation as quick reference designations. To date, that I am aware of, these designations have not been accepted by BellCore or the NOF.

You should also be aware that in the past some of these patterns had some rather colorful names such as “Trip Test.” There were two problem with

this:

1. The names were not specific enough. Several different patterns that in theory performed the same functions were circulated using the “Trip Test”

name. This caused several instances of technicians thinking there was a circuit problem, because either end of the circuit could run to the others loop but head-to-head tests wouldn’t work. The reality was, each end had a different “Trip Test” pattern loaded in their test sets.

2. At least one name used was crude, bordering on vulgar to some. This came out forcefully when a Telco employee took offense when the test pattern name was used during a conference call. Luckily, the situation was resolved before a formal complaint was filed with the FCC.

To prevent any recurrence of either of these situations, always refer to these patterns by their Octet, e.g., 55-Octet, or T1-x designation.

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T1-1/Hex 72-Octect Pattern [RtL]:

fr 80 80 80 80 01 00 01 01 01 03 80 01 80 01 01 80 01 22 00 20 22 00 20 AA

fr AA AA AA AA 55 55 55 55 AA AA AA AA 55 AA AA 55 55 55 80 80 FF FF FF FF

fr FF FF FF FE FF FF 24 49 92 88 88 88 10 42 08 21 84 20 08 82 40 20 10 80

Stresses repeater preamplifier and automatic line build out (ALBO) circuits on DS1s. Detects marginal equipment using rapid transitions from a low ones density to a high ones density. This pattern will invoke B8ZS if in use.

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T1-2/Hex 96-Octect Pattern [RtL]:

fr FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

fr FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

fr AA AA AA AA 80 01 80 01 80 01 80 01 80 01 80 01 80 01 80 01 80 01 80 01

fr AA AA AA AA 80 01 80 01 80 01 80 01 80 01 80 01 80 01 80 01 80 01 80 01

Primarily used for “Pattern Sensitivity” issues due to inductor hysteresis problems, and ALBO testing. Switches between maximum ones density, causing saturation, and low ones density. It also will stress very marginal power supplies and voltage regulators. This pattern will invoke B8ZS, if used.

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T1-3/Hex 54-Octect Pattern [RtL]:

fr 01 01 01 01 01 01 00 01 01 01 01 01 01 03 01 01 01 01 07 01 01 01 55 55

fr 55 55 AA AA AA AA 01 01 01 01 01 01 FF FF FF FF FF FF 80 01 80 01 80 01

fr 80 01 80 01 80 {Continues to repeat, shifting fr bit 5 bytes each time}

Detects marginal equipment with rapid shifts between short blocks of high- ones-density and low-ones-density sequences. It also provides high stress to timing recovery circuits. This pattern will invoke B8ZS if in use.

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T1-4/Hex 120-Octect hex pattern [RtL]:

fr FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

fr FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

fr FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

fr AA AA AA AA 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10

fr AA AA AA AA 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10

The T1-4 pattern is the ‘work around’ for the BellCore two minute limit on the all 1′s pattern. It provides extreme stress to power supplies and power regulators. It cycles between a long string of maximum ones density and very low ones density. This is also useful in finding ALBO problems and “Pattern Sensitivity” issues due to hysteresis problems with inductors.

Among the T1-x patterns, the 120-Octet is unique. Nowhere in this pattern are there more than seven zeros in a row, so it will NEVER cause B8ZS to invoke on equipment optioned for it. If the test set B8ZS indicator flashes when this pattern is run something is broken.

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T1-5/Hex 53-Octect Pattern [RtL]:

fr 80 01 80 01 80 01 80 01 80 01 80 01 80 01 80 01 80 01 80 01 80 01 80 01

fr 80 01 80 01 80 01 01 AF AA AF 01 01 01 01 FF FF FF FF 01 01 01 01 FF FF

fr FF FF FF FF CB {Continues to repeat, shifting fr bit 5 bytes each time}

Primarily a low-ones-density pattern, with two short bursts of high ones density. If this pattern causes steadily incrementing errors it points toward a timing recovery issue. If you see intermittent bursts of errors it is most likely an ALBO problem, or a very bad power supply or regulator.

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T1-6/Hex 55-Octect Pattern [RtL]: {Note: Modified Daly pattern, see T1-Daly}

**

fr 01 01 01 01 01 01 00 01 01 01 01 01 01 03 01 01 01 01 07 01 01 01 01 55

fr 55 55 55 AA AA AA AA 01 01 01 01 01 01 FF FF FF FF FF FF 80 01 80 01 80

fr 01 80 01 80 01 80 01 {Repeats, shifting the fr bit 7 bytes each time}

Stresses ALBO circuits, preamplifier, and equalization circuits of repeaters and timing recovery circuits of line cards. It changes rapidly from low-ones-density to high-ones-density sequences. This pattern most closely emulates DS0 data traffic within a PCM channelized DS1.

The framing bit will always fall at an octet boundary, never in the middle of a byte. Since the frame bit (fr) shifts position over time, it is possible to get 16 zeros in a row when a ’0′ frame bit falls between bytes seven (**) and eight. This violates the maximum zeros requirement for AMI facilities. So T1-6 should only be used on B8ZS coded facilities.

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T1-Daly/Hex 55-Octect Pattern [RtL]: {Original 55-Octet pattern, see T1-6}

**

fr 01 01 01 01 01 01 80 01 01 01 01 01 01 03 01 01 01 01 07 01 01 01 01 55

fr 55 55 55 AA AA AA AA 01 01 01 01 01 01 FF FF FF FF FF FF 80 01 80 01 80

fr 01 80 01 80 01 80 01 {Repeats, shifting the fr bit 7 bytes each time}

Mr. Tom Daly, of New England Telephone, developed this pattern to provide greater stress on DS1 circuits than the standard QRSS pattern. Some Telcos call this the 55-Octet pattern. If you are running 55-Octet head-to-head with Telco, and taking occasional bursts of errors or synch losses, verify you are both using the same pattern. Also, if dealing with a Telco that says they are not familiar with the 55-Octet pattern, try the “Daly pattern” name.

As with the T1-6 pattern, it stresses ALBO circuits, preamplifier, and equalization circuits of repeaters, and timing recovery circuits of line cards. The difference is, the original pattern developed by Mr. Daly contains hex 80 in byte seven (**) instead of 00. This means that as the frame bit (fr) shifts position over time, when it falls between bytes seven and eight there will never be more than 15 zeroes in a row, even if it is a ’0′. So if you want to run a 55-Octet test on AMI facilities, the T1-Daly should be the pattern of choice. It also works quite well on facilities with B8ZS line coding if you do not care if B8ZS is invoked.

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SPECIAL PURPOSE FIXED TEST PATTERNS

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“80 Zeros” Pattern:

Hex [RtL]

fr F9 FA FB FF FE AA AA AA 00 00 00 00 00 00 00 00 00 00 33 33 33 33 33 33

Binary [LtR]

fr 10011111 01011111 11011111 11111111 01111111 01010101 01010101 01010101

00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000

00000000 00000000 11001100 11001100 11001100 11001100 11001100 11001100

This pattern is specifically intended for checking the proper end-to-end operation of a DS1 circuit using B8ZS line coding. The name of this pattern comes from the 10 bytes of hex ’00′, which equal 80 binary zeros. It is exactly one DS1 frame in length, which means if input to the DS1 side of a PCM channel bank each channel will receive a constantly repeating byte. This can be useful when trouble shooting some Nx64 contiguous bandwidth problems.

The 80-Zeros pattern is very effective in finding AMI/B8ZS mismatches, AMI/AMI patches, and marginal DS1 ports on M13 DS2 and ECS1 DXC cards when run head-to-head. It contains enough ’1′s to provide timing recovery so equipment being tested doesn’t lock up.

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FOX Test Pattern: THE QUICK BROWN FOX JUMPS OVER THE LAZY DOG 0123456789

This is the standard asynchronous pattern for teletype communications.

It’s also useful in testing through MODEMs and DSUs set for asynchronous mode, and as the payload of synchronous protocols. It includes all of the upper case letters, and numbers 0 – 9.

On the TTC FireBerd 6000, this is the default pattern loaded in USER2 and USER3. The difference when using synchronous timing is USER2 is 7-bit ASCII and USER3 is 8-bit ASCII. In asynchronous mode, the test is sent according to the number of data bits specified in the character format. Specifically:

5 bits = Baudot

6 bits = BCDIC

7 bits = ASCII (Almost universal in non-IBM environments)

8 bits = EBCDIC (Very common to IBM equipment)

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SDLC Frame Simulation Pattern:

Hex [RtL]:

FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

7E FF 01 AF AF AF 80 01 80 01 80 01 80 01 FF FF FF FF FF 7E FF FF FF FF

FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

This pattern simulates a SDLC frame being transmitted on a DDS DS0 circuit using Data Mode Idle (DMI), where RTS is held high between data transmissions.

It will identify marginal OCU-DP and DS0-DP cards, and channel cards with “Pattern Sensitivity” problems with the SDLC protocol. It also provides high stress to power supplies, ALBO, and repeater equalization circuitry.

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